Bomb Jack Arcade : Has someone tried to port this to the MiST ?

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jerome777
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Bomb Jack Arcade : Has someone tried to port this to the MiST ?

Postby jerome777 » Mon Mar 13, 2017 12:46 pm

Hello to all VHDL, Verilog coders and MiST users !

Has someone ever tried to port this ?
http://papilio.cc/index.php?n=Playground.BombJack

There is a YouTube video on the page (part 5), but also the four parts before, showing the progression (made in 2012) :
https://www.youtube.com/user/d18c7db/videos

There is a section "Limitations" at the bottom the page : the use of 32 BRAM blocks, will probably make things harder.

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Newsdee
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Re: Bomb Jack Arcade : Has someone tried to port this to the MiST ?

Postby Newsdee » Tue Mar 14, 2017 1:24 am

I think the problem is the MiST SDRAM is not fast enough to multiplex ROM data.

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Re: Bomb Jack Arcade : Has someone tried to port this to the MiST ?

Postby Sorgelig » Tue Mar 14, 2017 6:42 am

MiST FPGA has 66(or 69? i forgot) BRAM blocks, although you can't compare BRAM blocks from different FPGA chips.

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Re: Bomb Jack Arcade : Has someone tried to port this to the MiST ?

Postby ijor » Tue Mar 14, 2017 12:19 pm

Xilinx BRAM (18 Kbit) is twice as big as MiST FPGA M9K. The problem as Newsdee is saying, might be external SRAM vs DRAM.

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Re: Bomb Jack Arcade : Has someone tried to port this to the MiST ?

Postby jotego » Tue Mar 21, 2017 5:19 pm

But it doesn't mean Bomb Jack cannot be done on MiST, right? It's just that particular implementation which has issues on MiST

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Re: Bomb Jack Arcade : Has someone tried to port this to the MiST ?

Postby ijor » Wed Mar 22, 2017 12:07 pm

jotego wrote:But it doesn't mean Bomb Jack cannot be done on MiST, right? It's just that particular implementation which has issues on MiST


Very difficult to tell without more details. But I can certainly conceive a similar hardware that won't fit on the MIST. If you have many subsystems each one accessing its own RAM or ROM at the same time, you might have a problem. As long as you have enough internal RAM it's ok. But otherwise, external DRAM might not be able to reproduce the behavior.

You can access only a single external RAM address at a time, and DRAM (contrary to SRAM) has a substantial latency for random access. MIST DRAM has a much faster bandwidth than old school memory. But depending on the case it might not be enough to compensate.


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