Open Source 68K Accelerator Project(s)

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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 6:18 pm

rpineau wrote:Our VHDL code for the 68020 using a Xilinx XC95144XL works so there might be something you're missing in your verilog code somewhere.
We will open source our code one we've fixed the remaining problems and have 32bit TOS working but in the mean time if you want to look at the code I can send it to you (it's VHDL).


I'm suspecting some sort of contact failure now but I could just compile your code straight against a my ucf and see what happens.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 6:30 pm

let me send you the code.
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 7:45 pm

OK i have discovered the issue.... DS is not asserted on the MFP. Fine... but i dont understand how Rodolphe's code works.

Using a multimeter i traced the LDS signal to the DS pin on the MFP.. so far so good.... i need to assert LDS and I am not....

My code for LDS is....

wire LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b001);

Which means its low except when trying to do a word access??

which i think is wrong... its been copied from a PAL equation probably and i think its inverted...

It should be....

wire LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b110);

Which means go low except when doing a byte access on the upper word...

I now see the DS at the MFP but no DTACK. The saga continues.......


Ignore section in quotes. I forgot for a moment the 68K is big endian.
Last edited by terriblefire on Tue Nov 29, 2016 8:04 pm, edited 1 time in total.

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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 8:02 pm

My last post is complete rubbish. i have no idea why but the CPU is interrupt acking on an ODD address?

I cant make out any difference between my code the VHDL .

Giving up for now. The MFP is getting a low DS and a high CS + I am seeing an IACK. But its not assering DTACK. IEI is low. IEO is high.
Last edited by terriblefire on Tue Nov 29, 2016 8:19 pm, edited 1 time in total.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 8:05 pm

the proper code (gal code) for UDS and LDS is :

!UDS = !DS00 & !A0;
!LDS = !DS00 & SIZ1
# !DS00 & !SIZ0
# !DS00 & A0;

DS00 is the 68020 delayed DS
I remember there was some error in AN944 (and I think LUCAS has the fixed code for this).
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 8:21 pm

Thats identical to what i have when you do de morgans on it.

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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 8:26 pm

Keep in mind this code works on an Amiga 500 perfectly. And i have a diagnostic rom that tests ram and interrupts on that machine.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 8:41 pm

LDS should go low on access to bit 8-15 of the data bus (which is what you see)
UDS should go low on access to bit 0-7 of data bus.
I don't know verilog but you have :
wire LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b110);

So when DS20 is 0 (LO) t, we assume that DS20DLY also is 0 (after the delay).
so DS20 | DS20DLY is 0 (LO)
{A0, SIZ[1:0]} == 3'b110 is a vector comparison .. which would return true .. and true is 1 ? and 0 | 1 is 1 .. LDS not going LO there .. or Am I missing something ?
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 8:45 pm

wire LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b001);

Is the correct one.

({A0, SIZ[1:0]} == 3'b001) is the condition for not asserting LDS. When this condition is met it will prevent the signal being asserted.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 8:50 pm

in VHDL I have
LDS <= not SIZ1 and SIZ0 and not A0;
so if I move these around to match your order :
LDS <= not A0 and not SIZ1 and SIZ0 ;
so indeed 0b001 but still, doesn't ({A0, SIZ[1:0]} == 3'b001) return 1 ?
in wich case you have 'x | x | 1' in the code, so the result is 1, not 0 so LDS doesn't go LO
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 8:59 pm

Now i am doubting myself again. :)

LDS <= not A0 and not SIZ1 and SIZ0 ;

= (for the case 001)

LDS <= (not 0) and (not 0) and (1) ; is 1.

So its the same.

I tried switching these and the ST didnt even execute more than 5 instructions...

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 9:27 pm

based on LDS <= not SIZ1 and SIZ0 and not A0;

Byte access to odd address:
SIZ1 = 0 , SIZ0 = 1, A0 = 1
LDS <=( not 0) and (1) and (not 1);
LDS <= 1 and 1 and 0;
LDS = 0 (LO)

UDS = A0 => UDS = 1 (HI)

Word access on even address :
SIZ1 = 1, SIZ0 = 0, A0 = 0
LDS <= (not 1) and (0) and (not 0);
LDS <= 0 and 0 and 1;
LDS = 0 (LO)

UDS = A0 => UDS = 0 (LO)


In VHDL the 'and' in a 'variable <= value' is a logic and ( 0 and x = 0), so I guess equivalent to & in verilog (and & or * in GAL asm).

so in my code we get LDS=0 and UDS=1 for byte access on odd address and LDS=0 and UDS=0 for word access on even address, as expected from a 68000 system.
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 9:33 pm

rpineau wrote:based on LDS <= not SIZ1 and SIZ0 and not A0;

Byte access to odd address:
SIZ1 = 0 , SIZ0 = 1, A0 = 1
LDS <=( not 0) and (1) and (not 1);
LDS <= 1 and 1 and 0;
LDS = 0 (LO)

UDS = A0 => UDS = 1 (HI)

Word access on even address :
SIZ1 = 1, SIZ0 = 0, A0 = 0
LDS <= (not 1) and (0) and (not 0);
LDS <= 0 and 0 and 1;
LDS = 0 (LO)

UDS = A0 => UDS = 0 (LO)


In VHDL the 'and' in a 'variable <= value' is a logic and ( 0 and x = 0), so I guess equivalent to & in verilog (and & or * in GAL asm).

so in my code we get LDS=0 and UDS=1 for byte access on odd address and LDS=0 and UDS=0 for word access on even address, as expected from a 68000 system.


This is the bit where i get confused.... From the manual....

Table 5-2. SIZ1, SIZ0 Signal Encoding
SIZ1 SIZ0 Size
Negated Asserted Byte (I.e. 1 0 )?
Asserted Negated Word (I.e. 0 1)?

Asserted means 0? Negated = 1? (my head is spinning now).

... In this section and in the remainder of the manual, assert and
negate are used to specify forcing a signal to a particular state.
In particular, assertion and assert refer to a signal that is active
or true; negation and negate indicate a signal that is inactive or
false. These terms are used independently of the voltage level
(high or low) that they represent.

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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 9:36 pm

But in any case...

LDS <= not SIZ1 and SIZ0 and not A0;

is identical to

LDS = ({A0, SIZ[1:0]} == 3'b001)

I could have written it as

LDS = ~A0 & ~SIZ[1] & SIZ[0];

Its a personal preference i have when dealing with long conditions to use values.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 9:38 pm

SIZ0 and SIZ1 are active HI .. so asserted means 1, not 0 (/DSACKx are active LO, so asserted means 0).
Also keep in mind... I'm not a VHDL guru or CPLD guru :) ..
I know our code works on a STE and MegaSTE (so probably on a STF too).
Our VHDL code is based on our previous CPLD code (using CUPL) which was also working.
I don't know verilog so all I'm saying is .. are we doing the same thing in both languages ? (aka trying to help :) ).
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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 9:41 pm

I agree with your last statement (LDS = ~A0 & ~SIZ[1] & SIZ[0];)
but what is the result of ({A0, SIZ[1:0]} == 3'b001) ... True ? and true is ... 1, not 0...
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 9:51 pm

Its the same. Write down the condition for both being true.

If i split it out...

LDS = A0 == 1'b0 & SIZ[1] == 1'b0 & SIZ[0] == 1'b1;

I think you are focusing on the condition the result is 1 when all of the other cases are important. The 001 case is the case where LDS is not asserted.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 10:46 pm

I more trying to understand what a==1 in verilog returns as your using a ( X == Y) in an equation.
if a=0, a==1 should return 0 ? so 0 & x = 0
if a=1, a==1should return 1 ? so 1 & x = x

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 10:58 pm

So .. based on this :
http://www.asic-world.com/verilog/opera ... _Operators

"Result is 0 (false) or 1 (true)"

so ({A0, SIZ[1:0]} == 3'b001) returns 1 (true) and when you do
LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b001);
you do
LDS_INT = 0 | 0 | 1;
.. so LDS is 1 ... when it should be 0.

so /LDS is never asserted (Aka set LO) and the MFP/DS never goes LO and the MFP never put the vector on the bus and doesn't assert DTACK.
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 11:02 pm

rpineau wrote:So .. based on this :
http://www.asic-world.com/verilog/opera ... _Operators

"Result is 0 (false) or 1 (true)"

so ({A0, SIZ[1:0]} == 3'b001) returns 1 (true) and when you do
LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b001);
you do
LDS_INT = 0 | 0 | 1;
.. so LDS is 1 ... when it should be 0.

so /LDS is never asserted (Aka set LO) and the MFP/DS never goes LO and the MFP never put the vector on the bus and doesn't assert DTACK.


BUt thats exactly the same for the VHDL equation you gave. Its 1 for that condition too.

EDIT: Try it in a simulator. Give it those values and 1 will appear.

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 11:09 pm

I'm not testing a bit field.
this :
LDS <= not SIZ1 and SIZ0 and not A0;
is like :
LDS_INT = ~SIZ1 & SIZ- & ~A0;


your ({A0, SIZ[1:0]} == 3'b001) would translate to something like
result <= 1 when (A0 = '0' and SIZ1 = '0' and SIZ0 ='1') else 0;
so this is returning the result of a test.
and you test is TRUE so the return code from the test is 1 (true).

coud you test :
LDS_INT = DS20 | DS20DLY | (~A0 & ~SIZ[1] & SIZ[0]);
(hopefully this syntax is ok)
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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 11:15 pm

terriblefire wrote:EDIT: Try it in a simulator. Give it those values and 1 will appear.


You mean in the simulator you get 1 for LDS .. well .. you should get 0 as LDS is active LO.
So if it's 1 it never get asserted .. no /DS, no /DTACK... no working int from MFP
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 11:34 pm

rpineau wrote:I'm not testing a bit field.
this :
LDS <= not SIZ1 and SIZ0 and not A0;
is like :
LDS_INT = ~SIZ1 & SIZ- & ~A0;


your ({A0, SIZ[1:0]} == 3'b001) would translate to something like
result <= 1 when (A0 = '0' and SIZ1 = '0' and SIZ0 ='1') else 0;
so this is returning the result of a test.
and you test is TRUE so the return code from the test is 1 (true).

coud you test :
LDS_INT = DS20 | DS20DLY | (~A0 & ~SIZ[1] & SIZ[0]);
(hopefully this syntax is ok)


Ok but what you are saying here is

result <= 1 when True else 0;

Which is what all logic is.

RESULT <= (CONDITION THAT REDUCES TO A SINGLE BIT).

Either that or I am completely missing what you are trying to say.

The equation you gave is 1 for 001.

I have seen people do this in software development when they completely failed to understand equations... they write

If X then Y = true else Y = false;

Which is the same as

X = Y;

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Re: Open Source 68K Accelerator Project(s)

Postby rpineau » Tue Nov 29, 2016 11:45 pm

yes, so
RESULT <=(CONDITION THAT REDUCES TO A SINGLE BIT).
in this case CONDITION THAT REDUCES TO A SINGLE BIT is 1
so RESULT = 1;
but we want RESULT = 0 (aka LDS =0 aka /LDS pin is LO).

and yes.. people make the usual mistake you describe .. I try not to :) (I do both logic stuff like GAL and VHDL and C/C++ coding ... and some ASM 68k).
so my
result <= 1 when True else 0;
was to demonstrate the WRONG case
We want
result <= 0 when True else 1;
aka assert LDS when our test is TRUE, aka set LDS to 0 when our test is TRUE.
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Re: Open Source 68K Accelerator Project(s)

Postby terriblefire » Tue Nov 29, 2016 11:54 pm

rpineau wrote:I'm not testing a bit field.
this :
LDS <= not SIZ1 and SIZ0 and not A0;
is like :
LDS_INT = ~SIZ1 & SIZ- & ~A0;

your ({A0, SIZ[1:0]} == 3'b001) would translate to something like
result <= 1 when (A0 = '0' and SIZ1 = '0' and SIZ0 ='1') else 0;
so this is returning the result of a test.



You are fundamentally confused here. "Returning the result of a test"? This stuff is synthed as logic gates. Its not executed as a program.

result <= 1 when (A0 = '0' and SIZ1 = '0' and SIZ0 ='1') else 0;

and

LDS_INT = ~SIZ1 & SIZ- & ~A0;

are logically identical.

Lets write out the truth table....

LDS_INT = ~SIZ1 & SIZ- & ~A0;

A0 | SIZ1 | SIZ0 = LDS
0 0 0 0
1 0 0 0
0 1 0 0
1 1 0 0
0 0 1 1
1 0 1 0
0 1 1 0
1 1 1 0

Now for my way.....

result <= 1 when (A0 = '0' and SIZ1 = '0' and SIZ0 ='1') else 0;

A0 | SIZ1 | SIZ0 = LDS
0 0 0 0
1 0 0 0
0 1 0 0
1 1 0 0
0 0 1 1
1 0 1 0
0 1 1 0
1 1 1 0

There is no difference.... write it out yourself if you think i'm wrong...

Infact I wrote my shorthand *by writing out the truth table*... which is something i was taught to do at university.

If you have 3 variable and 2 and operators then you will only have 1 row in the truth table that has a 1 in it.

and you test is TRUE so the return code from the test is 1 (true).

coud you test :
LDS_INT = DS20 | DS20DLY | (~A0 & ~SIZ[1] & SIZ[0]);
(hopefully this syntax is ok)


Ok but what you are saying here is

result <= 1 when True else 0;

Which is what all logic is.

RESULT <= (CONDITION THAT REDUCES TO A SINGLE BIT).

Either that or I am completely missing what you are trying to say.

The equation you gave is 1 for 001.

I have seen people do this in software development when they completely failed to understand equations... they write

If X then Y = true else Y = false;

Which is the same as

X = Y;


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